Role Overview

We are looking for a highly motivated Senior Engineer – EMIR Methodology to join the Physical Design and Signoff team. In this role, you will be responsible for developing, maintaining, and enhancing EMIR signoff methodologies for advanced-node SoC designs. You will work closely with Physical Design, CAD, Power, Package, Foundry, and EDA teams to drive scalable signoff flows, automation, methodology improvements, and robust power integrity closure. The ideal candidate should have strong expertise in EMIR signoff methodologies, power integrity concepts, tool enablement, and advanced-node implementation challenges.

What You'll Do

• Develop and maintain block-level and full-chip EMIR signoff methodologies for advanced-node designs.
• Define and improve static and dynamic IR drop and electromigration verification flows.
• Collaborate with Physical Design, CAD, Foundry, Package, and EDA vendors to drive methodology enhancements.
• Establish signoff guidelines, best practices, and quality metrics for EMIR closure.
• Develop automation frameworks, scripts, regression flows, and dashboards for EMIR analysis and reporting.
• Drive tool qualification, correlation, and deployment across projects and technology nodes.
• Support methodology adoption, documentation, training, and user enablement across design teams.
• Support tapeout activities and ensure robust EMIR signoff readiness.

What We're Looking For

• 5+ years of experience in EMIR Methodology, Power Integrity Signoff, CAD Methodology, or Physical Design Signoff.
• Strong understanding of static and dynamic IR drop analysis, electromigration concepts, power grid design, and signoff methodologies.
• Hands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, Apache RedHawk-SC, or equivalent, including methodology development and flow automation.

Good to Have

• Understanding of foundry-qualified EMIR signoff methodologies, reliability verification flows, and advanced-node design challenges.

Success in This Role Looks Like

• Robust and scalable EMIR methodologies deployed across multiple SoC programs.
• Improved signoff quality, runtime efficiency, and correlation across tools and technology nodes.
• Increased engineering productivity through automation and methodology enhancements.
• Successful enablement of advanced-node EMIR signoff requirements and timely tapeout execution.