Role Overview We are looking for a Senior Physical Design Engineer to own and drive the implementation of complex digital SoCs from synthesis through tapeout. You will work at the intersection of design and process, translating RTL into silicon-ready layouts that meet aggressive PPA targets. This role exists to ensure our chips are not only functionally correct but physically optimized, manufacturable, and delivered on schedule.

What You'll Do Lead floorplanning, placement, CTS, routing, and signoff for one or more design blocks or full-chip subsystems Drive timing closure across multiple corners and modes using industry-standard EDA tools (Cadence Innovus, Synopsys ICC2, or equivalent) Perform and interpret IR drop, EM, DRC, LVS, and antenna analyses; own resolution of violations Collaborate with RTL designers, DFT, and verification teams to ensure physical constraints align with design intent Work with foundry and PDK teams to validate design rules and address process-specific requirements Contribute to methodology improvements — scripts, flows, and automation to improve turnaround time and quality of results Mentor junior engineers and review their work at key implementation milestones What We're Looking For 5+ years of hands-on physical design experience on advanced-node designs (16nm or below preferred) Deep expertise in the full PD flow: floorplanning → placement → CTS → routing → signoff Strong understanding of timing analysis, STA constraints (SDC), and multi-corner multi-mode (MCMM) closure Proficiency with at least one major implementation tool suite (Cadence or Synopsys) and signoff tools (Tempus, PrimeTime, Voltus, RedHawk) Solid grasp of low-power design techniques — power gating, multi-voltage domains, UPF/CPF Experience working directly with foundry PDKs (TSMC, Samsung, or equivalent) through tapeout Good to Have Exposure to custom or mixed-signal blocks and interface IP integration (PCIe, DDR, USB) Scripting proficiency in Tcl, Python, or Perl for flow automation Prior experience in a tapeout lead or block owner role on a production chip Success in This Role Looks Like Blocks are delivered to signoff with PPA targets met — timing clean, no DRC/LVS violations, power within budget Tapeout milestones are hit on schedule with minimal late-stage surprises or re-spins attributable to physical implementation Flow and methodology improvements you drive measurably reduce runtime or improve QoR for the broader team Junior engineers grow faster and make fewer critical mistakes because of your technical guidance and code/design reviews