Role Overview

We are seeking an experienced Staff Engineer – Static Timing Analysis (STA) to lead timing analysis and signoff activities for complex SoC and advanced-node designs. In this role, you will drive timing closure across multiple blocks and full-chip designs, collaborate with cross-functional implementation teams, and contribute to STA methodology improvements. The ideal candidate should possess strong expertise in timing signoff, MMMC analysis, and advanced timing optimization techniques.

What You’ll Do

• Lead block-level and full-chip STA activities including setup, hold, recovery, removal, and noise analysis

• Drive timing closure across multiple modes and corners using MMMC methodologies

• Analyze and debug complex timing violations in collaboration with synthesis, CTS, P&R, and ECO teams

• Define and validate timing constraints including SDC generation, timing exceptions, and clock definitions

• Perform timing signoff using industry-standard STA tools and methodologies

• Drive ECO implementation and timing optimization with focus on performance, power, and area trade-offs

• Contribute to automation, methodology enhancement, and flow optimization initiatives

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline

• 7+ years of experience in STA, timing closure, or Physical Design signoff roles

• Strong understanding of STA concepts including OCV/AOCV/POCV, SI/noise analysis, clocking methodologies, and timing exceptions

• Hands-on experience with Synopsys PrimeTime and advanced timing signoff flows

• Good understanding of synthesis, CTS, place-and-route, extraction, and ECO implementation flows

• Strong scripting skills in Tcl, Perl, Python, or Shell for automation and productivity improvement

Good to Have

• Experience with advanced-node technologies such as 7nm, 5nm, or below

• Exposure to low-power design methodologies including UPF/CPF and power-aware STA

• Experience in full-chip timing convergence and successful tapeout execution for large SoC designs

Success in This Role Looks Like

• Achieving timing closure with robust signoff quality across all operating modes and corners

• Efficient resolution of complex timing issues with optimized performance, power, and area impact

• Improved STA productivity through automation and methodology enhancements

• Successful collaboration across implementation and signoff teams leading to timely tapeout execution

Location

Hybrid / On-site – Bengaluru / Remote - India