Role Overview

We are looking for a highly skilled Staff Physical Design Engineer to drive end-to-end physical implementation for advanced semiconductor designs across cutting-edge technology nodes. The ideal candidate will lead block/subsystem-level implementation activities, collaborate cross-functionally with RTL, STA, DFT, and CAD teams, and ensure high-quality tape-outs with strong focus on power, performance, and area (PPA). This role requires deep expertise in physical design methodologies, debugging complex issues, and mentoring junior engineers.

What You’ll Do

• Lead full-chip or block-level physical design implementation from floorplanning to GDS signoff.

• Drive floorplanning, power planning, placement, CTS, routing, optimization, and physical verification closure.

• Analyze and optimize timing, congestion, IR drop, EM, and power for advanced technology nodes.

• Collaborate with RTL, DFT, STA, package, and CAD teams to resolve implementation and signoff challenges.

• Develop and improve physical design flows, automation scripts, and methodology enhancements.

• Support tape-out activities and ensure design signoff quality across all implementation stages.

• Mentor junior engineers and contribute to technical reviews and best practices.

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.

• 8+ years of hands-on experience in ASIC/SOC physical design implementation.

• Strong expertise in industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, and StarRC.

• Solid understanding of timing closure, low-power design techniques, signal integrity, IR/EM analysis, and physical verification.

• Experience working on advanced technology nodes (7nm/5nm/3nm preferred).

• Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancement.

• Excellent debugging, problem-solving, communication, and stakeholder collaboration skills.

Good to Have

• Experience with hierarchical and top-level SOC integration.

• Exposure to ML/AI-based design optimization methodologies.

• Knowledge of package-aware implementation and multi-die/chiplet architectures.

Success in This Role Looks Like

• Consistent delivery of high-quality physical design milestones with minimal schedule impact.

• Successful closure of timing, power, area, and reliability metrics for complex SOC designs.

• Proactive identification and resolution of implementation bottlenecks and signoff risks.

• Positive contribution to team productivity, methodology improvements, and mentoring initiatives.